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document number: mc35xs3500 rev. 4.0, 5/2011 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, inc. , 2010-2011. all rights reserved. smart rear corner light switch (penta 35 m ) the 35xs3500 is designed for low-voltage automotive and industrial lighting applications. it s five low rds(on) mosfets (five 35 m ) can control the high sides of five separate resistive loads (bulbs and leds). programming, control, and diagnostics are accomplished using a 16-bit spi interface (3.3 v or 5.0 v). each output has its own pwm control via the spi. the 35xs3500 has highly sophisticated failure mode handling to provide high ava ilability of the outputs. its multiphase control and out put edge shaping improves electromagnetic compatibility (emc) behavior. the 35xs3500 is packaged in a power-enhanced 12 x 12 nonleaded power qfn package with exposed tabs. features ? penta 35 m high side switches ? 16-bit spi communication interface with daisy chain capability ? current sense output with spi-programmable multiplex switch and board temperature feedback ? digital diagnosis feature ? pwm module with multiphase feature including prescaler ? leds control including accurate current sensing and low duty- cycle capability ? fully protected switches ? over-current shutdown detection ? power net and reverse polarity protection ? low-power mode ? fail mode functions incl uding auto restart feature ? external smart power switch control including current recopy ? lead-free packaging designated by suffix code pna figure 1. 35xs3500 simpli fied application diagram high side switch 35xs3500 ordering information device temperature range (t a ) package MC35XS3500PNA -40 to 125 c 24 pqfn pna suffix 98art10511d 24-pin pqfn pb free bottom view mcu 35xs3500 limp flasher ign rst clock cs s0 si sclk csns gnd vcc vbat cp out1 out2 out3 out4 out5 fetin fetout watchdog vbat 12v 5.0v 12v smart switch stop
analog integrated circuit device data 2 freescale semiconductor 35xs350 internal block diagram internal block diagram figure 2. 35xs3500 simplified internal block diagram vcc vbat cp gnd over-temperature prewarning selectable output current logic internal regulator gate drive out1 csns cs so si sclk clock limp flasher ign out2 out1 out2 recopy (analog mux) out3 out3 out4 out5 fetin fetout driver for external mosfet out5 v cc failure open load over-temperature detection rst out4 r dwn over-current detection detection detection ov/uv/por detections charge drain/gate clamp pump stop temperature feedback r dwn r up vcc led control current recopy synchronization
analog integrated circuit device data freescale semiconductor 3 35xs3500 pin connections pin connections figure 3. 35xs3500 pin connection s (transparent package top view) table 1. 35xs3500 pin definitions functional descriptions these pins can be found in the functional description section beginning on page 18 . pin pin name pin function formal name definition 1 fetin input external fet input this pin is the current sense re copy of the external mosfet. 2 ign input ignition input (active high) this input wakes the device. it also controls outputs 1 and 2 in case of fail mode activation. this pin has a passive internal pull-down. 3 rst input reset this input wakes the device. it is also used to initialize the device configuration and fault registers thr ough the spi. this pin has a passive internal pull-down. 4 flasher input flasher input (active high) this input wakes the device. this pin has a passive internal pull-down. 5 clock input clock input this pin state depends on rst logic level. as long as rst input pin is set to logic [0], this pin is pulled up in order to report wake event. otherwise, the pwm frequency and timing are generated from this digital cl ock input by the pwm module. this pin has a passive internal pull-down. 6 limp input limp home input (active high) the fail mode can be activated by this digital input. this pin has an active internal pull-down current source. 7 stop input stop light input (active high) this input wakes the device. this pin has a passive internal pull-down. 8 cs input chip select (active low) when this signal is high, spi signals are ignored. asserting this pin low starts a spi transaction. the transac tion is signaled as completed when this signal returns high. this pin has a passive internal pull-up resistance. 9 sclk input spi clock input this input pin is connected to the ma ster microcontroller providing the required bit shift clock for spi comm unication. this pin has a passive internal pull-down resistance. 13 24 12 10 9 8 7 6 5 4 3 2 1 11 23 22 19 20 21 16 17 18 15 14 cp gnd out5 out4 out3 out2 out1 gnd csns fetout so vcc si sclk cs stop limp clock flasher rst ign fetin gnd vbat
analog integrated circuit device data 4 freescale semiconductor 35xs350 pin connections 10 si input master-out slave-in this data input is sampled on the posit ive edge of the sclk. this pin has a passive internal pull-down resistance. 11 vcc input logic supply spi logic power supply. 12 so output master-in slave-out spi data sent to the mcu by this pin. this data output changes on the negative edge of sclk, and when cs is high. this pin is high-impedance. 13 fetout output external fet gate this pin controls an external smart mosfet by logic level. this output called out6. if out6 is not used in the application, this output pin is set to logic high when the current sense output becomes valid when csns sync spi bit is set to logic [1]. 14, 17, 23 gnd ground ground this pin is the ground for the logic and analog circuitry of the device. (1) 15 vbat input battery input power supply pin. 16 cp output charge pump this pin is the connection for an exter nal tank capacitor (for internal use only). 18 19 20 21 22 out5 out4 out3 out2 out1 output output output output output output 5 output 4 output 3 output 2 output 1 protected 35 m high side power output to the load. 24 csns output current sense output this pin is used to output a current proportional to out1:out5, fet in current, and it is used externally to generate a ground-referenced voltage for the microcontroller to monitor output current. moreover, this pin can report a voltage proportional to the temperature on the gnd flag. out1:out5, fet in current sensing and temperature feedback choice is spi programmable. notes 1. the pins 14, 17, and 23 must be shorted on the board. table 1. 35xs3500 pin definitions (continued) functional descriptions these pins can be found in the functional description section beginning on page 18 . pin pin name pin function formal name definition
analog integrated circuit device data freescale semiconductor 5 35xs3500 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. rating symbol value unit electrical ratings over-voltage test range maximum operation voltage load dump (400 ms) @ 25 c v bat 28 40 v reverse polarity voltage range 2.0 min @ 25 c v bat - 18 v vcc supply voltage v cc -0.3 to 5.5 v output voltage positive negative (ground disconnected) v out 40 -16 v digital input current in clamping mode (si, sclk, cs , ign, flasher, stop, limp) i in 1.0 ma fetin input current i fetin +10 -1.0 ma so and fetout output voltage v so - 0.3 to v cc + 0.3 v outputs clamp energy usi ng single pulse method (l = 2.0 mh; r = 0 ; vbat = 14 v @ 150 c initial) e 30 mj esd voltage (2) human body model (hbm) out[1:5], vpwr, and gnd charge device model (cdm) corner pins (1,13,19,21) all other pins (2-12, 14-18, 20, 22-24) v esd 2000 8000 750 500 v thermal ratings operating temperature ambient junction t a t j - 40 to 125 - 40 to 150 c peak pin reflow temperature during solder mounting (3) t solder 260 c storage temperature t stg - 55 to 150 c thermal resistance thermal resistance, junction to case (4) r jc 1.0 c/w notes 2. esd testing is performed in accordanc e with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ) and the charge device model. 3. pin soldering temperature limit is for 40 seconds maximum durat ion. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. if the qualification fails, ts older will be changed for 240 c. 4. typical value is guaranteed per design.
analog integrated circuit device data 6 freescale semiconductor 35xs350 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electrical characteristics characteristics noted under conditions 3.0 v v cc 5.5 v, 7.0 v v bat 20 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit power input (vbat, vcc) battery supply voltage range full performance and short circuit extended voltage range (5) v bat 7.0 6.0 ? ? 20 28 v battery supply under-voltage (uv flag is set on) v batuv 5.0 5.5 6.0 v battery voltage clamp (ov flag is set on) v batclamp_ov 27.5 30 32.5 v battery voltage clamp v batclamp 40 ? 48 v battery supply power on reset (8) if v bat < 5.5 v, v bat = v cc if v bat < 5.5 v, v bat = 0 v batpor1 v batpor2 2.0 2.0 ? ? 3.0 4.0 v vbat supply current @ 25 c and v bat =12 v and v cc = 5.0 v sleep state current, outputs open sleep state current, outputs grounded normal mode, ign = 5.0 v, rst = 5.0 v, outputs open i batsleep1 i batsleep2 i bat ? ? ? 0.5 0.5 10 5.0 5.0 20 a a ma digital voltage range, full performance v cc 3.0 ? 5.5 v digital supply under-voltage (vcc failure) v ccuv 2.2 2.5 2.8 v sleep current consumption on v cc @ 25 c and v bat = 12 v output off i ccsleep ? 0.2 5.0 a supply current consumption on v cc and v bat = 12 v no spi 3.0 mhz spi communication i cc ? ? ? ? 2.6 5.0 ma logic input/ output (ign, cs , csns, si, sclk, clock, so, flasher, rst , limp, stop) input high logic level (6) v ih 2.0 ? ? v input low logic level (6) v il ? ? 0.8 v ignition threshold level (ign, flasher, stop and rst ) v ign th 1.0 2.2 v input clamp voltage (ign, flasher, limp, stop, cs , sclk, si, rst ) i = 1.0 ma v cl_pos 7.5 ? 13 v input forward voltage (ign, flasher, limp, stop, cs , sclk, si, rst ) i = 1.0 ma v cl_neg - 2.0 ? -0.3 v input passive pull-up resistance on cs pin (7) r up 100 200 400 k input passive pull-down resistance on si, sclk, flasher, ign, fog, clock, limp and rst pins (7) r dwn 100 200 500 k so high-state output voltage i oh = 1.0 ma v soh 0.8 0.95 ? v cc notes 5. in extended mode, the functionality is guaranteed but not the electrical parameters. 6. valid for rst , si, sclk, clock, flasher, stop, and limp pins. 7. valid for the following input voltage range: vcc = -0.3 to +0.3 v. 8. please refer to loss of vbat section for more details.
analog integrated circuit device data freescale semiconductor 7 35xs3500 electrical characteristics static electrical characteristics logic input/ output (ign, cs , csns, si, sclk, clock, so, flasher, rst , limp, stop) (continued) clock output voltage reporting wake-up event (i clock =1.0 ma) v clockh 0.8 0.95 ? v cc so low-state output voltage i ol = -1.6 ma v sol ? 0.2 0.4 v so tri-state leakage current cs > 0.7 v cc i soleak - 1.0 0.0 1.0 a csns tri-state leakage current vcc = 5.5 v, csns = 5.5 v vcc = 5.0 v, csns = 5.5 v vcc = 5.0 v, csns = 4.5 v i csnsleak - 5.0 - 10 - 1.0 0 0 0 1.0 1.0 1.0 a current sense output clamp voltage i csns < 10.0 ma v csns 5.0 6.0 7.0 v output (out 1:5) output leakage current in off state sleep mode, outputs grounded normal mode, outputs grounded i outleak ? ? 0 20 2.0 25 a output negative clamp voltage i out = -500 ma, outputs off v out - 22 ? -16 v current sense output precision (9) full-scale range (fsr) for led control bit = 0 0.75 fsr 0.50 fsr 0.25 fsr 0.10 fsr full-scale range (fsr) for led control bit = 1 0.187 fsr = 0.75 fsr led 0.125 fsr = 0.50 fsr led 0.062 fsr = 0.25 fsr led 0.025 fsr = 0.10 fsr led i cs / i cs -14 -15 -17 -22 -13 -13 -20 -30 - - - - - - - - 14 15 17 22 13 13 20 30 % current sense output precision over-temperature range [-40;125 c], v bat range [10 v-16 v] and fsr range [25%-100%], calculated with one calibration point (taken at 25 c, vbat = 13.5 v and 50% fsr) (11) -6.0 - 6.0 % current sense output precision wi th one calibration point (50% fsr led , v bat = 13.5 at 25 c (11) -6.0 ? 6.0 % temperature drift of current sense output (10) v bat = 13.5 v, i out = 2.8 a reference taken at t a = 25 c i cs / t ? 280 400 ppm/ c minimum output current reported in csns for out[1-5] (12) 10 v vbat 16 v i 35min(csns) 65 ? ? ma minimum output current reported in csns for out[1-5] in led mode (12) 10 v vbat 16 v i 35min(csns) led 40 ? ? ma notes 9. 10 v < v bat < 16 v. ( i cs / i cs = (measured i cs - targeted i cs )/ targeted i cs with targeted i cs = 5.0 ma 10. based on statistical data. not production tested. i cs / t = [(measured at i cs at t 1 - measured at i cs at t 2 ) measured at i cs at room]/ (t 1 - t 2 ) 11. based on statistical analysis covering 99.74% of parts. 12. output current value computed after leakage current removal (open load condition) table 3. static electrica l characteristics (continued) characteristics noted under conditions 3.0 v v cc 5.5 v, 7.0 v v bat 20 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 8 freescale semiconductor 35xs350 electrical characteristics static electrical characteristics output (out 1:5) (continued) over-temperature shutdown t ots 155 175 195 c thermal prewarning (13) t otswarn 110 125 140 c output voltage threshold v out_th 0.475 0.5 0.525 v bat tail light (out1) output drain-to-source on resistance (i out = 2.8 a, t a = 25 c) v bat = 13.5 v v bat = 7.0 v r ds(on) ? ? ? ? 35 55 m output drain-to-source on resistance (i out = 2.8 a, v bat = 13.5 v, t a = 150 c) (13) r ds(on) ? ? 59.5 m reverse output on resistance (i out = -2.8 a, v bat = -12 v, t a = 25 c) (14) r sd(on) ? ? 70 m tail light (out1) output drain-to-source on resistance (i out = 1.5 a, t a = 25 c) for led control = 1 v bat = 13.5 v v bat = 7.0 v r ds(on)25_led ? ? ? ? 70 110 m output drain-to-source on resistance (i out = 1.5 a, v bat = 13.5 v, t a = 150 c) for led control = 1 r ds(on)150_led ? ? 119 m high over-current shutdown threshold 1 v bat = 16 v, t a = -40 c v bat = 16 v, t a = 25 c v bat = 16 v, t a = 125 c i ochi1 28.0 30.2 29.4 28.3 35.0 36.0 35.0 33.8 43.5 41.8 40.6 39.3 a high over-current shutdown threshold 2 i ochi2 12.3 15.4 18.5 a low over-current shutdown threshold i oclo 5.7 7.2 8.9 a open load current threshold in on state (15) i ol 0.05 0.2 0.5 a open load current threshold in on state with led (16) v ol = v bat - 0.5 v i olled 4.0 10 20 ma current sense full-scale range (17) i cs fsr ? 6.0 ? a current sense full-scale range (13) depending on led control = 1 i cs fsr_led ? 1.6 ? a severe short-circuit impedance range (13) r sc1(out1) 350 m notes 13. parameter guaranteed by design; however it is not production tested. 14. source-to-drain on resistance (reverse drain-to -source on resistance) with negative polarity v bat . 15. olled1, bit d0 in si data is set to [0] 16. olled1, bit d0 in si data is set to [1] 17. for a typical value of i cs fsr, i csns = 5.0 ma. if the range is exceeded, no current clamp and the precision is not guaranteed. table 3. static electrical characteristics (continued) characteristics noted under conditions 3.0 v v cc 5.5 v, 7.0 v v bat 20 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 35xs3500 electrical characteristics static electrical characteristics license light (out2) output drain-to-source on resistance (i out = 2.8 a, t a = 25 c) v bat = 13.5 v v bat = 7.0 v r ds(on) ? ? ? ? 35 55 m output drain-to-source on resistance (i out = -2.8 a, v bat = -13.5 v, t a = 25 c) (22) r ds(on) ? ? 59.5 m reverse output on resistance (i out = 2.8 a, v bat = 12 v, t a = 150 c) (18) r sd(on) ? ? 70 m output drain-to-source on resistance (i out =1.5 a, t a = 25 c) for led control = 1 v bat = 13.5 v v bat = 7.0 v r ds(on)25_led ? ? ? ? 70 110 m output drain-to-source on resistance (i out = 1.5 a, v bat = 13.5 v, t a = 150 c) for led control = 1 r ds(on)150_led ? ? 119 m high over-current shutdown threshold 1 v bat = 16 v, t a = -40 c v bat = 16 v, t a = 25 c v bat = 16 v, t a = 125 c i ochi1 28.0 30.2 29.4 28.3 35.0 36.0 35.0 33.8 43.5 41.8 40.6 39.3 a high over-current shutdown threshold 2 i ochi2 12.3 15.4 18.5 a low over-current shutdown threshold i oclo 5.7 7.2 8.9 a open load current threshold in on state (19) i ol 0.05 0.2 0.5 a open load current threshold in on state with led (20) v ol = v bat - 0.5 v i olled 4.0 10 20 ma current sense full-scale range (21) i cs fsr ? 6.0 ? a current sense full-scale range (22) depending on led control = 1 i cs fsr_led ? 1.6 ? a notes 18. source-to-drain on resistance (reverse drain-to -source on resistance) with negative polarity v bat . 19. olled2, bit d0 in si data is set to [0] 20. olled2, bit d0 in si data is set to [1] 21. for typical value of i cs fsr , i csns = 5.0 ma. if the range is exceeded, no current clamp and the precision is not guaranteed. 22. parameter guaranteed by design; however, it is not production tested. table 3. static electrical characteristics (continued) characteristics noted under conditions 3.0 v v cc 5.5 v, 7.0 v v bat 20 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 35xs350 electrical characteristics static electrical characteristics license light (out2) (continued) severe short-circuit impedance range (23) r sc1(out2) 350 m tail light (out3) output drain-to-source on resistance (i out = 2.8 a, t a = 25 c) v bat = 13.5 v v bat = 7.0 v r ds(on)25 ? ? ? ? 35 55 m output drain-to-source on resistance (i out = 2.8 a, v bat = 13.5 v, t a = 150 c) (23) r ds(on)150 ? ? 59.5 m reverse source-to-drain on resistance (i out = -2.8 a, v bat = -12 v, t a = 25 c) (24) r sd(on)25 ? ? 70 m output drain-to-source on resistance (i out = 1.5 a, t a = 25 c) for led control = 1 v bat = 13.5 v v bat = 7.0 v r ds(on)25_led ? ? ? ? 70 110 m output drain-to-source on resistance (i out = 1.5 a, v bat = 13.5 v, t a = 150 c) for led control = 1 r ds(on)150_led ? ? 119 m high over current shutdown threshold 1 v bat = 16 v, t a = -40 c v bat = 16 v, t a = 25 c v bat = 16 v, t a = 125 c i ochi1 28.0 30.2 29.4 28.3 35.0 36.0 35.0 33.8 43.5 41.8 40.6 39.3 a high over-current shutdown threshold 2 i ochi2 12.3 15.4 18.5 a low over-current shutdown threshold i oclo 5.7 7.2 8.9 a open load current threshold in on state (25) i ol 0.05 0.2 0.5 a open load current threshold in on state with led (26) v ol = v bat - 0.5 v i olled 4.0 10 20 ma current sense full-scale range (27) i cs fsr ? 6.0 ? a current sense full-scale range (22) depending on led control = 1 i cs fsr_led ? 1.6 ? a severe short-circuit impedance range (23) r sc1(out3) 350 m notes 23. parameter guaranteed by design; however, it is not production tested. 24. source-to-drain on resistance (reverse drain-to -source on resistance) with negative polarity v bat . 25. olled3, bit d2 in si data is set to [0] 26. olled3, bit d2 in si data is set to [1] 27. for a typical value of i cs fsr, i csns = 5.0 ma. if the range is exceeded, no current clamp and the precision is not guaranteed. table 3. static electrical characteristics (continued) characteristics noted under conditions 3.0 v v cc 5.5 v, 7.0 v v bat 20 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 35xs3500 electrical characteristics static electrical characteristics stop light (out4) output drain-to-source on resistance (i out = 2.8 a, t a = 25 c) v bat = 13.5 v v bat = 7.0 v r ds(on)25 ? ? ? ? 35 55 m output drain-to-source on resistance (i out = 2.8 a, v bat = 13.5 v, t a = 150 c) (28) r ds(on)150 ? ? 59.5 m output drain-to-source on resistance (i out = 1.5 a, t a = 25 c) for led control = 1 v bat = 13.5 v v bat = 7.0 v r ds(on)25_led ? ? ? ? 70 110 m output drain-to-source on resistance (i out =1.5 a, v bat = 13.5 v, t a = 150 c) for led control = 1 r ds(on)150_led ? ? 119 m reverse source-to-drain on resistance (i out = -2.8 a, v bat = -12 v, t a = 25 c) (29) r ds(on)25 ? ? 70 m high over-current shutdown threshold 1 v bat = 16 v, t a = -40 c v bat = 16 v, t a = 25 c v bat = 16 v, t a = 125 c i ochi1 28.0 30.2 29.4 28.3 35.0 36.0 35.0 33.8 43.5 41.8 40.6 39.3 a high over-current shutdown threshold 2 i ochi2 12.3 15.4 18.5 a low over-current shutdown threshold i oclo 5.7 7.2 8.9 a open load current threshold in on state (30) i ol 0.05 0.2 0.5 a open load current threshold in on state with led (31) v ol = v bat - 0.5 v i olled 4.0 10 20 ma current sense full-scale range (32) i cs fsr ? 6.0 ? a current sense full-scale range (22) depending on led control = 1 i cs fsr_led ? 1.6 ? a severe short-circuit impedance range (28) r sc1(out4) 350 m flasher (out5) output drain-to-source on resistance (i out = 2.8 a, t a = 25 c) v bat = 13.5 v v bat = 7.0 v r ds(on)25 ? ? ? ? 35 55 m output drain-to-source on resistance (i out = 2.8 a, v bat = 13.5 v, t a = 150 c) (28) r ds(on)150 ? ? 59.5 m reverse source-to-drain on resistance (i out = -2.8 a, v bat = -12 v, t a = 25 c) (29) r sd(on)25 ? ? 70 m notes 28. parameter guaranteed by design; however, it is not production tested. 29. source-to-drain on resistance (reverse drain-to -source on resistance) with negative polarity v bat . 30. olled3, bit d2 in si data is set to [0] 31. olled3, bit d2 in si data is set to [1] 32. for a typical value of i cs fsr, i csns = 5.0 ma. if the range is exceeded, no current clamp and the precision is not guaranteed. table 3. static electrical characteristics (continued) characteristics noted under conditions 3.0 v v cc 5.5 v, 7.0 v v bat 20 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 35xs350 electrical characteristics static electrical characteristics flasher (out5) (continued) output drain-to-source on resistance (i out =1.5 a, t a = 25 c) for led control = 1 v bat = 13.5 v v bat = 7.0 v r ds(on)25_led ? ? ? ? 70 110 m output drain-to-source on resistance (i out = 1.5 a, v bat = 13.5 v, t a = 150 c) for led control = 1 r ds(on)150_led ? ? 119 m high over current shutdown threshold 1 v bat = 16 v, t a = -40 c v bat = 16 v, t a = 25 c v bat = 16 v, t a = 125 c i ochi1 28.0 30.2 29.4 28.3 35.0 36.0 35.0 33.8 43.5 41.8 40.6 39.3 a high over-current shutdown threshold 2 i ochi2 12.3 15.4 18.5 a low over-current shutdown threshold i oclo 5.7 7.2 8.9 a open load current threshold in on state (34) i ol 0.05 0.2 0.5 a open load current threshold in on state with led (35) v ol = v bat - 0.5 v i olled 4.0 10 20 ma current sense full-scale range (36) i cs fsr ? 6.0 ? a current sense full-scale range (22) depending on led control = 1 i cs fsr_led ? 1.6 ? a severe short-circuit impedance range (33) r sc1(out5) 350 m spare (fetout , fetin) fetout output high level @ i = 1.0 ma v h max 0.8 ? ? v cc fetout output low level @ i = 1.0 ma v h min ? 0.2 0.4 v fetin input full scale range current i fet in ? 5.0 ? ma fetin input clamp voltage v clin 5.3 ? 7.0 v drop voltage between fetin and csns for mux[2:0] = 110 i fet in = 5 ma, 5.5 v > csns > 0.0 v v drin 0.0 ? 0.4 v fetin leakage current when external current switch sense is enabled vcc > v fet in > 0 v, 5.5 v > vcc 4.5 v, csns open vcc > v fet in > 0 v, 4.5 v > vcc > 0, csns open i fetinleak - 1.0 - 1.0 ? ? 5.0 1.0 a temperature of gnd flag analog temperature feedback at t a = 25 c with 5.0 k > r csns > 500 v t_feed 920 1025 1140 mv analog temperature feedback derating with 5.0 k > r csns > 500 (33) v dt_feed 10.9 11.3 11.7 mv/ c analog temperature feedback precision (33) v dt_acc -15 ? 15 c analog temperature feedback precision with calibration point at 25 c (33) v dt_acc_cal -5.0 ? 5.0 c notes 33. parameter guaranteed by design; however, it is not production tested. 34. olled3, bit d2 in si data is set to [0] 35. olled3, bit d2 in si data is set to [1] 36. for a typical value of i cs fsr, i csns = 5.0 ma. if the range is exceeded, no current clamp and the precision is not guaranteed. table 3. static electrical characteristics (continued) characteristics noted under conditions 3.0 v v cc 5.5 v, 7.0 v v bat 20 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 13 35xs3500 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 4.5 v v cc 5.5 v, 7.0 v v bat 20 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit power outputs timing (out1:5) current sense valid time on resistive load only (39) sr bit = 0 sr bit = 1 t csns(val) ? ? 90 45 150 75 s current sense synchronization time on fetout sr bit = 0 sr bit = 1 t csns(sync) ? ? 130 70 185 110 s current sense settling time on resistive load only (39) t csns(set) ? 10 30 s driver output positive slew rate (30% to 70% @ v bat = 14 v) sr bit = 0, i out = 2.8 a sr bit = 1, i out = 0.7 a sr r 0.10 0.20 0.25 0.40 0.56 0.80 v/ s driver output negative slew rate (70% to 30% @ v bat = 14 v) sr bit = 0, i out = 2.8 a sr bit = 1, i out = 0.7 a sr f 0.10 0.20 0.25 0.40 0.56 0.80 v/ s driver output matching slew rate (sr r /sr f )(70% to 30% @ v bat = 14 v @ 25 c) sr 0.8 1.0 1.2 driver output turn-on delay (spi on command [no pwm, cs positive edge] to output = 50% v bat @ v bat = 14 v) sr bit = 0, i out = 2.8 a sr bit = 1, i out = 0.7 a t dlyon 50 25 ? ? 120 65 s driver output turn-off delay (spi off command [ cs positive edge] to output = 50% v bat @ v bat = 14 v) sr bit = 0, i out = 2.8 a sr bit = 1, i out = 0.7 a t dlyoff 50 25 ? ? 120 65 s driver output matching time ( t dly(on) - t dly(off) ) @ output = 50% v bat with v bat = 14 v, f pwm = 240 hz, pwm = 50%, @ 25 c t rf - 30 ? 30 s pwm module nominal pwm frequency range (39) f pwm 30 ? 400 hz clock input frequency range f clk 7.68 ? 51.2 khz output pwm duty cycle maximum range for 11 v analog integrated circuit device data 14 freescale semiconductor 35xs350 electrical characteristics dynamic electrical characteristics watchdog timing watchdog timeout (spi failure) t wdto 50 75 100 ms i /o plausibility check timing fault shutdown delay time (from over-temperature or ochi1 or ohci2 or oclo fault detection to output = 50% v bat without round shaping feature for turn off) t sd ? 7.0 30 s under-voltage deglitch time (41) t uv 1.5 2.5 5.0 s high over-current threshold time 1 t 1 7.0 10 13.5 ms high over-current threshold time 2 t 2 52.5 75 97.5 ms autorestart period t autorst 52.5 75 97.5 ms autorestart over-current shutdown delay time t ocsh_auto 3.5 5.0 6.5 ms limp home input pin deglicher time t limp 7.0 10.0 13.0 ms cyclic open load detection timing with led (42) t olled 105 150 195 ms flasher toggle timeout t flasher 1.4 2.3 3.0 s ignition toggle timeout t ignition 1.4 2.3 3.0 s stop toggle timeout t stop 1.4 2.3 3.0 s clock input low frequency detection range f lclk det 1.0 2.0 4.0 khz clock input high frequency detection range f hclk det 100 200 400 khz spi interface characteristics maximum frequency of spi operation f spi ? ? 3.0 mhz rising edge of cs to falling edge of cs (required setup time) (43) t cs ? ? 1.0 us falling edge of cs to rising edge of sclk (required setup time) (43) t lead ? ? 500 ns required high state duration of sclk (required setup time) (43) t wsclkh ? ? 167 ns required low state duration of sclk (required setup time) (43) t wsclkl ? ? 167 ns falling edge of sclk to rising edge of cs (required setup time) (43) t lag ? 50 167 ns si to falling edge of sclk (required setup time) (44) t si su ? 25 83 ns falling edge of sclk to si (required setup time) (44) t si hold ? 25 83 ns notes 41. this time is measured from the v bat(uv) level to the fault reporting. parameter guaranteed in testmode. 42. olledn bit (where ?n? corresponds to respective outputs 1 through 5) in si data is set to logic [1]. refer to table 8, serial input address and configuration bit map , page 25 . 43. maximum setup time required for the 35xs3500 is the minimum guaranteed time needed from the microcontroller. 44. rise and fall time of incoming si, cs , and sclk signals suggested for des ign consideration to prevent t he occurrence of double pulsing. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 4.5 v v cc 5.5 v, 7.0 v v bat 20 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 15 35xs3500 electrical characteristics dynamic electrical characteristics spi interface characteristics (continued) so rise time c l = 80 pf t rso ? 25 50 ns so fall time c l = 80 pf t fso ? 25 50 ns si, cs , sclk, incoming signal rise time (45) t rsi ? ? 50 ns si, cs , sclk, incoming signal fall time (45) t fsi ? ? 50 ns time from falling edge of cs to so low-impedance (46) t so(en) ? ? 145 ns time from rising edge of cs to so high-impedance (47) t so(dis) ? 65 145 ns notes 45. time required for output status data to be available for use at so. 1.0 k on pull-up on cs . 46. time required for output status data to be terminated at so. 1.0 k on pull-up on cs . 47. time required to obtain valid data out from so following the rise of sclk. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 4.5 v v cc 5.5 v, 7.0 v v bat 20 v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 16 freescale semiconductor 35xs350 electrical characteristics timing diagrams timing diagrams figure 4. input timing switching characteristics figure 5. sclk waveform and valid so data delay time si csb sclk don?t care don?t care don?t care valid valid vih vil vih vih vil vil vil twrstb tlead twsclkh trsi tlag tsisu twsclkl tsi(hold) tfsi 0.7 vdd 0.7vdd 0.2vdd 0.2vdd 0.7vdd 0.7vdd tcsb tenbl sclk si cs 10% v cc t lead t wsclkh t rsi 90% v cc 10% v cc t si(su) t wsclkl t si(hold) t fsi 90% v cc t lag v ih v il v il v ih v il v ih v il t enbl t cs 90% v cc 10% v cc so so sclk voh vol voh vol voh vol tfsi tdlylh tdlyhl t valid trso tfso 3.5v 50% trsi high-to-low 1.0v 0.7 vdd 0.2vdd 0.2 vdd 0.7 vdd low-to-high t rsi t fsi 90% v cc sclk so so v oh v ol v oh v ol v oh v ol 0.8 v 10% v cc 90% v cc t rso t fso 10% v cc t so(en) t so(dis) 2.0 v low to high high to low t valid
analog integrated circuit device data freescale semiconductor 17 35xs3500 electrical characteristics timing diagrams figure 6. output slew rate and time delays figure 7. current sensing time delays v pwr v out[1:5] t dly(on) t dly(off) low logic level 70% v pwr 30% v pwr sr f sr r 50%v pwr r pwm cs high logic level v out[1:5] time time time i max i out[1:5] t dly(on) t csns(set) low logic level cs high logic level i csns time time time t csns(val) v fetout time low logic level high logic level t dly(off) with csns sync bit = 1 t csns(sync)
analog integrated circuit device data 18 freescale semiconductor 35xs350 functional description introduction functional description introduction the 35xs3500 is designed for low-voltage automotive and industrial lighting applications. its five low r ds(on) mosfets (five 35 m ) can control the high sides of five separate resistive loads (bulbs). programming, control, and diagnostics are accomplished using a 16-bit spi interface. functional pin description supply voltage (vbat) the vbat pin of the 35xs3500 is the power supply of the device. in addition to its supply function, this tab contributes to the thermal behavior of the device by conducting the heat from the switching mosfets to the printed circuit board. supply voltage (vcc) this is an external voltage in put pin used to supply the spi digital portion of the circuit and the gate driver of the external smart mosfet. ground (gnd) this pin is the ground of the device. clock input (clock) and pwm module when the part is in normal mode ( rst =1), the pwm frequency and timing are generated from the rising edge of clock input by the pwm module. the clock input frequency is the selectable factor 2 7 = 128 or 2 8 = 256 of the pwm frequency per output, depending pr bit value. the out1:6 can be controlled in the range of 4% to 96% with a resolution of 7 bits of duty cycle (bits d[6:0]). the following table describes the pwm resolution. table 5. pwm resolution the timing includes four programmable pwm switching phases (0, 90, 180, and 270) to improve overall emc behavior of the light module. the amplitude of the input current is divided by four while the frequency is 4 times the original one. the two following pictures illustrate the behavior. the synchronization of the switching phases between different corner light ic is provided by a spi command in combination with the cs input. the bit in the spi is called pwm sync (initialization register). in normal mode, no pwm feature (100% duty cycle) is provided in the following instances: ? with the following spi co nfiguration: d7:d0=ff. ? in case of clock input signal failure (out of f pwm ), the outputs state depends on the d7 bit value (d7=1+on) in normal mode. in fail mode. the output s state depends on the ign, stop and flasher pins. if rst =0, this pin reports the wake-up event for wake=1 when vbat and vcc are in operational voltage range. limp home (limp) the limp home mode of the component can be activated by this digital input port. the signal is ?high active?, meaning the fail mode can be activated by a logic high signal at the input. on/off (bit d7) duty cycle (7 bits resolution) output state 0 x off 1 0000000 pwm (1/128 duty cycle) 1 0000001 pwm (2/128 duty cycle) 1 0000010 pwm (3/128 duty cycle) 1 1111111 fully on ch.1 ch.2 ch.3 ch.4 total 0 90 180 270 0 ch.1 ch.2 ch.3 ch.4 total 0 90 180 270 0
analog integrated circuit device data freescale semiconductor 19 35xs3500 functional description functional pin description ignition input (ign) the ignition input wakes the device. it also controls the fail home mode activation. the signal is ?high active?, meaning the component is active in case of a logic high at the input. flasher input (flasher) the flasher input wakes the device. it also controls the fail mode activation. the signal is ?high active?, meaning the component is active in case of a logic high at the input. reset input ( rst ) this input wakes the device when the rst pin is at logic [1]. it is also used to initialize the device configuration and the spi fault registers when the signal is low. all si/so registers described in table 8 and table 11 are reset. the fault management is not affected by rst (see figure 2 ). current sense output (csns) the current sense output pin is an analog current output or a voltage proportional to the temperature on the gnd flag. the routing to the common resistor is spi programmable. this current sense monitori ng may be synchronized in case of the out6 is not used. so, the current sense monitoring can be synchronized with a rising edge on the fetout pin (t csns(sync) ) if csns sync spi bit is set to logic [1]. connection of the fetout-p in to a mcu input pin allows the mcu to sample the csns-pin during a valid time-slot. since this falling edge is generated at the end of this time- slot, upon a switch-off command, this feature may be used to implement maximum current control. charge pump (cp) an external capacitor is connected between this pin and the vbat pin. it is used as a tank for the internal charge pump. its typical value is 100 nf 20%, 25 v maximum. fetout output (fetout) this output pin is used to control an external mosfet (out6). the high level of the fetout output is vcc if v bat and v cc are available in case of fetout is controlled on. fetout is not protected in case of a short circuit or under- voltage on v bat . in case of a reverse battery, out6 is off. fetin input (fetin) this input pin gives the curr ent recopy of the external mosfet. it can be routed on the csns output by a spi command. spi protocol description the spi interface has a full-duplex, three-wire synchronous data transfer with four i /o lines associated with it: serial clock (sclk), serial input (si), serial output (so), and chip select ( cs ). the si/so pins of the 35xs3500 device follow a first-in, first-out (d15 to d0) protoc ol, with both input and output words transferring the most significant bit (msb) first. all inputs are compatible with 5.0 v cmos logic levels supplied by v cc . the spi lines perform the following functions: serial clock (sclk) the sclk pin clocks the internal shift registers of the 35xs3500 device. the si pin accepts data into the input shift register on the falling edge of the sclk signal, while the so pin shifts data information out of the so line driver on the rising edge of the sclk signal. it is important that the sclk pin be in a logic low state whenever cs makes any transition. for this reason, it is recommended that the sclk pin be in a logic [0] whenever the device is not accessed ( cs logic [1] state). sclk has a passive pull-down, r dwn . when cs is logic [1], signals at the sclk and si pins are ignored and so is tri-stated (high-impedance) (see figure 8 ).
analog integrated circuit device data 20 freescale semiconductor 35xs350 functional description functional pin description figure 8. single 16-bit word spi communication serial input (si) the si pin is a serial interface command data input pin. each si bit is read on the falling edge of sclk. a 16-bit stream of serial data is required on the si pin, starting with d15 to d0. si has a passive pull-down, r down . serial output (so) the so data pin is a tri-state ou tput from the shift register. the so pin remains in a high-impedance state until the cs pin is put into a logic [0] state. the so data is capable of reporting the status of the ou tput, the device configuration, and the state of the key inputs. the so pin changes state on the rising edge of sclk and r eads out on the falling edge of sclk. chip select ( cs ) the cs pin enables communication with the master device. when this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the master device. the 35xs3500 device latches in data from the input sh ift registers to the addressed registers on the rising edge of cs . the device transfers status information from the power output to the shift register on the falling edge of cs . the so output driver is enabled when cs is logic [0]. cs should transition from a logic [1] to a logic [0] state only when sclk is a logic [0]. cs has a passive pull-up, r up . stop input (stop) the stop input wakes the device. it also controls the fail mode activation. the signal is ?high active?, meaning the component is active in case of a logic high at the input. cs csb si sclk so d15 d1 d2 d3 d4 d5 d6 d7 d8 d9 d14 d13 d12 d11 d10 od12 d0 od13 od14 od15 od6 od7 od8 od9 od10 od11 od1 od2 od3 od4 od5 1. rstb is in a logic h state during the above operation. 2. do, d1, d2, ... , and d15 relate to the most recent ordered entry of program data into the lux ic 3 od0 od1 od2 and od15 relate to the first 16 bits of ordered fault and status data out of the lux ic notes: od0 cs device. device. 1. d15:d0 relate to the most recent ordered entry of data into the device. 2. od15:od0 relate to the first 16 bits of ordered fault and status data out of the device. notes
analog integrated circuit device data freescale semiconductor 21 35xs3500 functional device operation operational modes functional device operation operational modes sleep mode the sleep mode is the default mode of the 35xs3500. this is the state of the devic e after first applying battery voltage (v bat ) and prior to any i /o transitions. this is also the state of the device when ign, rst , flasher, and stop are logic [0]. in the sleep mode, the output and all internal circuitry are off to minimize current draw. in addition, all spi-configurable features of the device are reset. the 35xs3500 will transit to two modes (normal and fail) depending on wake and fail signals (see table 18, watchdog window ). the transition to the other modes is according to the following signals: ?wake = ign or ign_on or flasher or flasher_on or stop or stop_on or rst ?fail = vcc fail or spi fail or external limp normal mode the 35xs3500 is in normal mode when: ?wake = 1 ?fail = 0 i n normal operating mode the power outputs are under full control of the spi as follows: ? the outputs 1 to 6, including multiphase timing, and selectable slew-rate, are controlled by the programmable pwm module. ? the output 4 is activated dire ctly by the stop external pin in case the stop_en bit is set to a logic [1]. ? the outputs 1 to 5 are switched off in case of under- voltage on vbat. ? the outputs 1 to 5 are protec ted by the selectable over- current double window and ov er-temperature shutdown circuit. ? the digital diagnosis featur e transfers status of the smart outputs via the spi. ? the analog current sense output (current recopy feature) can be rerouted by the spi. ? the outputs can be configur ed to control led loads: r ds(on) is increased by a factor of 2 and the current recopy ratio is scaled by a factor of 4. ? the spi reports nm=1 in this mode. the following figure describes the pwm, outputs and over- current behavior in normal mode. fail mode the 35xs3500 is in fail mode when: ?wake = 1 ?fail = 1 in fail mode: ? the outputs are under control of the external pins (see table 5). ? the outputs are fully protec ted in case of overload, over-temperature and under-voltage (on b vat or on v cc ). ? the spi reports continuously the content of address 11, disregard to previous requested output data word. ? neither digital diagnosis feature (spi) nor analog current sense are available. ? in case of overload (ochi2 or oclo) conditions or under-voltage on vbat, the outputs are under control of the autorestart feature. ? in case of a serious overload condition (ochi1 or ot) the corresponding output is latched off until a new wake-up event (wake = 0 then 1) over-current output d0-d6 bits d7 bit over-current out[1,2] ign (external) ign_on 1.4 sec min table 6. limp home output state output 1 tail light output 2 license light output 3 rear drive light output 4 stop light output 5 flasher external switch rear fog light ign pin off off stop pin flasher pin off
analog integrated circuit device data 22 freescale semiconductor 35xs350 functional device operation operational modes autorestart strategy the autorestart circuitry is used to supervise the outputs and reactivate high side switches in case of overload or under-voltage failure conditions, and provide a high availability of the outputs. this autorestart is available in fail mode when no supervising intelligence of the microcontroller is available. autorestart is activated in case of an overload condition (ochi2 or oclo) or under-voltage condition on vbat ( table 9, over-current window in case of autorestart ). the autorestart switches on the outputs. during the on state of the switch ochi1, the window is enabled for tochi_auto, then after the output is protected by oclo. figure 9. over-current window in case of autorestart in case of ochi1 or ot, the switch is latched off until wake up (wake=0, then 1). in case of oclo or under-voltage, the output switch is off. after the autor estart period (75 ms) is turned on again. in case an under-voltage occurred in fail mode, it will be latched and delatched after the auto restart period (t autorst ). the autorestart is not limited in time. transition fail to normal mode to leave the fail mode, the fail condition must be removed (fail=0). the microcontroller has to toggle the spi d10 bit (0 to 1) to reset to the watchdog bit; the other bits are not considered. the previous latc hed faults are reset by the transition into normal mode. transition normal to fail mode to leave the normal mode, a fail condition must occur (fail=1). the previous latched f aults are reset by the transition into fail mode. if the si is shorted to vcc, the device transmits to fail safe mode until the wd bit to ggles through t he spi (from [0] to [1]). all settings are according to predefined values (all bits set to logic [0]). start-up sequence the 35xs3500 enters into normal mode after start-up if the following sequence is provided: ?v bat and v cc power supplies must be above their under-voltage thresholds (sleep mode). ? generate a wake-up event (wake=1) from 0 to 1 on rst . the device switches to normal mode. ? apply the pwm clock after a maximum of 200 s (min. 50 s). ? send a spi command to the device status register to clear the clock fail flag and enable the pwm module to start. if the correct startup sequenc e is not provided, the pwm function is not guaranteed. figure 10 describes the wake-up block diagram. power off mode the 35xs3500 is in power off mode when the battery voltage is below v batpor[1,2] thresholds. for more details, please refer to loss of vbat paragraph. output current ochi1 oclo time tochi_auto auto period oclo or uv fault
analog integrated circuit device data freescale semiconductor 23 35xs3500 functional device operation operational modes figure 10. operating modes state machine notes: * only available in case of vcc fail condition wake=(rst =1) or (ign_on=1) or (flasher_on=1) or (stop_on=1) fail=(vcc_fail=1) or (spi_fail=1) or (ext_limp=1) sleep (fail=0) and (wake=1) (wake=0) fail normal (wake=0) (fail=1) and (wake=1) (fail=0) and (wake=1) (wake=1) and (fail=1) * power off v bat > v batpor[1,2] v bat < v batpor[1,2] v bat < v batpor[1,2] v bat < v batpor[1,2]
analog integrated circuit device data 24 freescale semiconductor 35xs350 functional device operation operational modes figure 11. wake-up block diagram internal regulator fault management pwm freq detector oscillator spi registers pwm module rst fog ign vbat vcc dig2.5v wake-up bar fog_on ign_on wake fail spi fail vcc fail external limp or deglitcher deglitcher reset flasher flasher_on deglitcher external_on external external: ign, flasher, fog external_on: ign_on , flasher_on, fog_on 1.4 sec min clock uvf or vcc vbat
analog integrated circuit device data freescale semiconductor 25 35xs3500 functional device operation logic commands and registers logic commands and registers serial input communication spi communication compliant to 3.3 v and 5.0 v is accomplished using 16-bit messages. a message is transmitted by the master star ting with the msb, d15, and ending with the lsb, d0. each incoming command message on the si pin can be interpreted using the bit assignment described in table 7 . the 5 bits d15 : d11, called register address bits, are used to select the command register. bit d10 is the watchdog bit. the remaining 10 bits, d9 : d0, are used to configure and control t he output and its protection features. multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable or to conf irm transmitted data as long as the messages are all multiples of 16 bits. any attempt made to latch in a message that is not 16 bits will be ignored. all spi registers are reset (all bits equal 0) in case of rst equals 0 or fail mode (fail=1). device register addressing the register addresses (d15 : d11) and the impact of the serial input registers on device operation are described in this section. table 8 summarizes the content of the si registers. address 00000 ? initialization the initialization register is used to read the various statuses, choose one of the six outputs current recopy, enable the stop pin, and synchronize the switching phases table 7. si message bit assignment bit sig si msg bit message bit description msb d15 : d11 register address bits. d10 watchdog in: toggled to satisfy watchdog requirements. lsb d9 : d0 used to configure inputs, outputs, device protection features, and so status content. table 8. serial input address and configuration bit map si register si address si data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 initialization 0 0 0 0 0 wd 0 0 stopen pwm sync 0 mux2 mux1 mux0 soa1 soa0 config ol 0 0 0 0 1 wd led control5 led control4 led control3 led control2 led control1 olled 5 olled 4 olled 3 olled 2 olled 1 config prescaler 0 0 0 1 0 wd 0 pr1 pr2 pr3 0 0 0 pr4 pr5 pr6 config sr 0 0 0 1 0 wd 1 sr1 sr2 sr3 0 0 0 sr4 sr5 0 config csns 0 0 0 1 1 wd csns sync 0 0 0 0 no_ochi5 no_ochi4 no_ochi3 no_ochi2 no_ochi1 control out1 0 1 0 0 1 wd phase2 phase1 onoff pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 control out2 0 1 0 1 0 wd phase2 phase1 onoff pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 control out3 0 1 0 1 1 wd phase2 phase1 onoff pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 control out4 0 1 1 0 0 wd phase2 phase1 onoff pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 control out5 0 1 1 0 1 wd phase2 phase1 onoff pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 control external switch 0 1 1 1 0 wd phase2 phase1 onoff pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 reset x x x x x 0 0 0 0 0 0 0 0 0 0 0 note: testmode address used only by fsl is d[15:11]=01111 with rst voltage higher than 8v typ.
analog integrated circuit device data 26 freescale semiconductor 35xs350 functional device operation logic commands and registers between different corner light de vices. the register bits d1 and d0 determine the content of the 16 bits of so data. (refer to the section entitled serial output communication (device status return data) beginning on page 27 .) bits d9 : d2 are described in table 9 . the watchdog timeout is specified by the t wdto parameter. as long as the wd bit (d10) of an incoming spi message is toggled within the minimum watchdog timeout period (wdto), the device will operate normally. if an internal watchdog timeout occurs before the wd bit is toggled, the device will revert to fail mode. all registers are cleared. to exit the fail mode, send valid spi communication with wd bit = 1. table 9. initialization register address 00001 ? configuration ol the configuration ol register is used to enable the open load detection for leds in normal mode (olledn in table 8 , page 25 ) and to active the led control. when bit d0 is set to logic [1], the open load detection circuit for led is activated for output 1. when bit d0 is set to logic [0], open load detection circuit for standard bulbs is activated for output 1. when bit d5 is set to logic [1], the led control is activated for output 1. address 00010 ? configuration prescaler and sr two configuration registers are available at this address. the configuration prescaler when d9 bit is set to logic [0] and configuration sr when d9 bit is set to logic [1]. the configuration prescaler r egister is used to enable the pwm clock prescaler per output. when the corresponding pr bit is set to logic [1], the clock presca ler (reference clock divided by 2) is activated for the dedicated output. the sr prescaler register is used to increase the output slew-rate by a factor of 2. when the corresponding sr bit is set to logic [1], the output switching time is divided by 2 for the dedicated output. address 00011 ? configuration csns the configuration current sense register is used to disable the high over-curr ent shutdown phase (ochi1 and ochi2 dynamic levels) in order to activate immediately the current sense analog feedback. when bit d9 is set to logic [1], the current sense synchronization signal is reported on fetout output pin. when the corresponding no_ochi bit is set to logic [1], the output is only protected wit h oclo level. and the current sense is immediately available if it is selected through spi, as described in figures 13 . the no_ochi bit per output is automatically reset at each corresponding on off bit transition from logic [1] to [0] and in case of over-temperature or over-current fault. all no_ochi bits are also reset in case of under-voltage fault detection. address 01001 ? control out1 bits d9 and d8 control the switching phases as shown in table 10 . bit d7 at logic [1] turns on out1. out1 is turned off with bit d7 at logic [0]. this register allows the master to control the duty cycle and the switching phases of out1. the duty cycle resolution is given by bits d6 : d0. d7 = 0, d6 : d0 = xx output off. si address si data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 wd 0 0 stopen pwm sync 0 mux2 mux1 mux0 soa1 soa0 x = don?t care d6 (pwm sync) = 0, no synchronization d6 (pwm sync) = 1, synchronization on csb positive edge d7 (stopen) = 0, stop pin does not control the output 4. d7 (stopen) = 1, stop pin controls the output 4. d4, d3, d2 (mux2, mux1, mux0) = 000, no current sense d4, d3, d2 (mux2, mux1, mux0) = 001, out1 current sense d4, d3, d2 (mux2, mux1, mux0) = 010,current sense d4, d3, d2 (mux2, mux1, mux0) = 011, out3 current sense d4, d3, d2 (mux2, mux1, mux0) = 100, out4 current sense d4, d3, d2 (mux2, mux1, mux0) = 101, out5 current sense d4, d3, d2 (mux2, mux1, mux0) = 110, external switch current sense d4, d3, d2 (mux2, mux1, mux0) = 111, temperature analog feedback table 10. switching phases d9 : d8 pwm phase 00 0 01 90 10 180 11 270
analog integrated circuit device data freescale semiconductor 27 35xs3500 functional device operation logic commands and registers d7 = 1, d6 : d0 = 00 output on during 1/128. d7 = 1, d6 : d0 = 1 a output on during 27/128 on pwm period. d7 = 1, d6 : d0 = 7 f output continuous on (no pwm). address 01010 ? control out2 same description as out1. address 011111 ? control out3 same description as out1. address 01100 ? control out4 same description as out1. address 01101 ? control out5 same description as out1. address 01110 ? control external switch same description as out1. address 01111 ? test mode this register is reserved for test and is not available with the spi during normal operation. serial output communication (device status return data) when the cs pin is pulled low, the output register is loaded. meanwhile, the data clo cks out the msb first as the new message data is clocked into the si pin. the first 16 bits of data clocking out of the so, and following a cs transition, is dependant upon the previous ly written spi word (soa1 and soa0 defined in the last spi initialization word). any bits clocked out of the so pin after the first 16 will be representative of the initial me ssage bits clocked into the si pin, since the cs pin first transitioned to a logic [0]. this feature is useful for daisy chaining devices. a valid message length is determined following a cs transition of logic [0] to logic [1]. if the message length is valid, the data is latched into t he appropriate registers. a valid message length is a multiple of 16 bits. at this time, the so pin is tri-stated and the fault status register is now able to accept new fault status information. the output status register corre ctly reflects the status of the initialization-selected regist er data at the time that the cs is pulled to a logic [0] during spi communication and / or for the period of time since the la st valid spi communication, with the following exceptions: ? the previous spi communication was determined to be invalid. in this case, the status will be reported as though the invalid spi communication never occurred. ? battery transients below 6. 0v, resulting in an under- voltage shutdown of the output s, may result in incorrect data loaded into the spi register, except the uvf fault reporting (od13). serial output bit assignment the contents of bits od15 : od0 depend on bits d1: d0 from the most recent initiali zation command soa[1:0] (refer to table 8 , page 25 ), as explained in the paragraphs that follow. the register bits are reset by a read operation and also if the fault is removed. table 11 summarizes the so register content. bit od10 reflects normal mode (nm). table 11. serial output bi t map description status / mode previous si data so data so a1 so a0 od1 5 od1 4 od13 od12 od11 od1 0 od9 od8 od7 od6 od5 od4 od3 od2 od1 od0 output status 0 0 0 0 uvf otw ots nm ol5 ovl5 ol4 ovl4 ol3 ovl3 ol2 ovl2 ol1 ovl1 overload status 0 1 0 1 uvf otw ots nm oc5 ots5 oc4 ots4 oc3 ots3 oc2 ots2 oc1 ots1 device status 1 0 1 0 uvf otw ots nm 0 ov stop _on flas her_ on ign_ on rc stop pin flasher pin ign pin clock fail output status 1 1 1 1 uvf otw ots nm 0 0 x x x out5 out4 out3 out2 out1 reset x x 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
analog integrated circuit device data 28 freescale semiconductor 35xs350 functional device operation logic commands and registers previous address soa[1:0] = 00 if the previous two l sbs are 00, bits od15 : od0 reflect the output status ( table 12 ). previous address soa[1:0] = 01 if the previous two lsbs are 01, bits od15 :o d0 reflect reflect the temperature status ( table 13 ). previous address soa[1:0] = 10 if the previous two l sbs are 01, bits od15 : od0 reflect the status of the 35xs3500 ( table 14 ). table 12. output status od15 od14 od13 od12 od11 od10 od9 od8 od7 od6 od5 od4 od3 od2 od1 od0 0 0 uvf otw ots nm ol5 ovl5 ol4 ovl4 ol3 ovl3 ol2 ovl2 ol1 ovl1 od13 (uvf) = under-voltage flag on v bat od12 (otw) = over-temperature prewarning flag od11 (ots) = over-temperature flag for all outputs od10 (nm) = normal mode od9, od7, od5, od3, od1 (ol5, ol4, ol3, ol2, ol1) = open load flag at outputs 5 through 1, respectively. od8, od6, od4, od2, od0 (ovl5, ovl4, ovl3, ovl2, ovl1) = overload flag for outputs 5 through 1, respectively.this corresponds to over-temperature or ochi or oclo faults. note a logic [1] at bits od9:od0 indicates a fault. if there is no fault, bits od9:od0 are logic [0]. ovl=ochi1+ochi2+oclo table 13. overload status od15 od14 od13 od12 od11 od10 od9 od8 od7 od6 od5 od4 od3 od2 od1 od0 0 1 uvf otw ots nm oc5 ots5 oc4 ots4 oc3 ots3 oc2 ots2 oc1 ots1 od13 (uvf) = under-voltage flag on v bat od12 (otw) = over-temperature prewarning flag od11 (ots) = over-temperature flag for all outputs od10 (nm) = normal mode od9, od7, od5, od3, od1 (oc5, oc4, oc3, oc2, oc1) = high over-current shutdown flag for outputs 5 through 1, respectively od8, od6, od4, od2, od0 (ots5, ots4, ots3, ots2, ots1) = over-temperature flag for outputs 5 through 1, respectively note a logic [1] at bits od9:od0 indicates a fault. if there is no fault, bits od9:od0 are logic [0]. oc=ochi1+ochi2 table 14. device status od15 od14 od13 od12 od11 od10 od9 od8 od7 od6 od5 od4 od3 od2 od1 od0 1 0 uvf otw ots nm 0 ov stop_ on flash er_on ign_o n rc stop pin flash er pin ign pin clock fail od13 (uvf) = under-voltage flag on v bat od12 (otw) = over-temperature prewarning flag od11 (ots) = over-temperature flag for all outputs od10 (nm) = normal mode od8 (over-voltage) = over-voltage flag on v bat in real time od7 = indicates the state of internal stop_on signal, as described in figures 11 od6 = indicates the state of internal flasher_on signal od5 = indicates the state of internal ign_on signal od4 (rc) = logic [0] indicates a front corner light switch. logic [1] indicates a rear corner light switch od3 (stop pin) = indicates the stop pin state in real time od2 (flasher pin) = indicates the flasher pin state in real time od1 (ign pin) = indicates the ign pin state in real time od0 (clock fail) = logic [1], which indicates a clock failure
analog integrated circuit device data freescale semiconductor 29 35xs3500 functional device operation logic commands and registers previous address soa[1:0] = 11 if the previous two l sbs are 11, bits od15 : od0 reflect the status of the 35xs3500 ( table 14 ). protection and diagnosis output protection features the 35xs3500 provides the fo llowing protection features: ? protection against transients on v bat supply line (per iso 7637) ? active clamp, including protection against negative transients on output line ? over-temperature ? severe and resistive over-current ? open load during on state these protections are provided for each output (out1:5). over-temperature detection the 35xs3500 provides over-temperature shutdown for each output (out1:out5 ). it can occur when the output pin is in the on or off state. an over-temperature fault condition results in turning off the corresponding output. the fault is latched and reported via the spi. to delatch the fault and be able to turn the outputs on again, the failure condition must be removed (t< 175 c typically) and: ? if the device was in normal mode, the output corresponding register (bit d7) must be rewritten. application of the complete ochi window (ochi1+ochi2 during t2) depends on toggling or not toggling d7 bit. ? if the device was in fail mode, the corresponding output is locked until device restart: wake up from sleep mode or v batpor1 . the spi fault report (ots bit) is removed after a read operation. over-current detections the 35xs3500 provides inte lligent over-current shutdown (see figure 12 ) in order to protect the internal power transistors and the harness in the event of overload (fuse characteristic). figure 12. double over-current window in normal mode ochi (i ochi1 and then i ochi2 ) is only activated after toggling the d7 bit in normal mode. during the output switching, the severe short-circuit condition provided on the module connector is reported as an ochi fault. in fail mode, the control of ochi window is provided by the toggles: ign_on, flasher_on. the current thresholds (i ochi1 , i ochi2 and i oclo ) and the time (t 1 and t 2 ) are fixed numbers for each driver. after t 2, the oclo current threshold is set to protect in steady state. t 1 and t 2 times are compared to ?on? state duration (t on ) of the output. in case of the output is controlled in pwm mode during the inrush period, the t on corresponds to the sum of each ?on? state duration in order to expand dynamically the transient over-current profile. in case of an overload (ochi1 or ochi2 or oclo detection), the corresponding out put is disabled immediately. the fault is latched and the status is reported via the spi. to delatch the fault, the failure condition must be removed and: for ochi1: ? if the device was in no rmal mode: the output corresponding register (bit d7) must be rewritten d7=1. application of complete ochi window d epends on toggling or not toggling d7 bit. table 15. output status od15 od14 od13 od12 od11 od10 od9 od8 od7 od6 od5 od4 od3 od2 od1 od0 1 1 uvf otw ots nm 0 0 x x x out5 out4 out3 out2 out1 od13 (uvf) = under-voltage flag on v bat od12 (otw) = over-temperature prewarning flag od11 (ots) = over-temperature flag for all outputs od10 (nm) = normal mode od4 (out5) = logic [0] indicates the out5 voltage is lower than v out_th . logic [1] indicates the out5 voltage is higher than v out_th od3 (out4) = logic [0] indicates the out4 voltage is lower than v out_th . logic [1] indicates the out4 voltage is higher than v out_th od2 (out3) = logic [0] indicates the out3 voltage is lower than v out_th . logic [1] indicates the out3 voltage is higher than v out_th od1 (out2) = logic [0] indicates the out2 voltage is lower than v out_th . logic [1] indicates the out2 voltage is higher than v out_th od0 (out1) = logic [0] indicates the out5 voltage is lower than v out_th . logic [1] indicates the out1 voltage is higher than v out_th ochi1 ochi2 oclo output current time t1 t2
analog integrated circuit device data 30 freescale semiconductor 35xs350 functional device operation logic commands and registers ? if the device was in fail mode, the failure is locked until restart of the device: wake-up from sleep mode or v batpor1 . for ochi2 and oclo: ? if the device was in normal mode: the output corresponding register (bit d7) must be rewritten d7=1. application of complete ochi window depends on toggling or not toggling d7 bit. ? if the device was in fail mo de, autorestart is activated. the device autorestart feature provides a fixed duty cycle and fixed period with ochi1 window. autorestart feature resets ochi2 or oclo fault after corresponding autorestart period. the spi fault reports are removed after a read operation: - oc bit=(ochi1) or (ochi2) fault - ovl bit=(ochi1) or (ochi2) or (oclo) fault over-voltage detection and active clamp the 35xs3500 provides an active gate clamp circuit, in order to limit the maximum drain to source voltage. in case of overload on an output, the corresponding switch (out[1 to 5]) is turned off which leads to a high voltage at vbat, with an inductive v bat line. the maximum vbat voltage is limited at v batclamp by active clamp circuitry through the load. in case of open load condition, the positive transient pulses (iso 7637 pulse 2 and inductive battery line) shall be handled by the application. figures 13 and 14 describe the faults management in normal mode and fail mode.
analog integrated circuit device data freescale semiconductor 31 35xs3500 functional device operation logic commands and registers off ochi1 ochi2 oclo (ochi2=1) or (ot=1) or (uv=1) or (d7=0) (ochi1=1) or (ot=1) or (uv=1) or (d7=0) d7=0 then 1 without fault and (no_ochi=0) (rewrite d7=1) and (t on t 1 without fault and (rewrite d7=1) and (no_ochi=0) (t on >t 2 ) and (rewrite d7=1) without fault (oclo=1) or (ot=1) or (uv=1) or (d7=0) note: t1 and t2 please refer to figure 12 . d7=0 then 1 without fault and (no_ochi=1) (no_ochi=1) without fault (no_ochi=1) without fault t 1 analog integrated circuit device data 32 freescale semiconductor 35xs350 functional device operation logic commands and registers figure 13. faults management in normal mode (for out[1:5] only) figure 14. faults management in fail mode (for out[1:5] only) diagnosis open load the 35xs3500 provides open load detection for each output (out1:out5 ) when the output pin is in the on state. open load detection levels can be chosen by the spi to detect a standard bulb or leds (olled bit). open load for leds only is detected during each regular switch-off state or periodically each t olled (fully-on, d[6:0] = 7f) . to detect olled in fully on state, the ou tput must be on at least t olled. when an open load has been det ected, the output stays on. to delatch the diagnosis, the condition should be removed and a spi read operation is needed (ol bit). in case of a power on reset on vbat, the fault will be reset. current sense the 35xs3500 diagnosis for load current (out1:6) is done using the current sense (csns) pin connected to an external resistor. the csns resistance value is defined in function to vcc voltage value. it is recommended to use resistor 500 < r csns < 5.0 k . typical value is 1.0 k for 5.0 v application. the routing of the current sense sources is spi programmable (mux[2,0] bits). the current recopy feature for out1:5 is disabled during a high over-current shutdown phase (t 2 ) and is only enabled during low over-current shutdown thresholds. the current recopy output delivers current only during on time of the output switch without over shoot (aperiodic settling). the current recopy is not active in fail mode. off out: off autorestart=0 ochi1 out: external ochi2 out: external oclo out: external (external_on=1) (t>t ochi1 ) and (autorestart=0) off-latched state off autorestart out: off autorestart=1 (ot=1) or (ochi1=1) (ot=1) (ot=1) (t>t ochi2 ) and (autorestart=0) (uv=1) or (ochi2=1) (oclo=1) or (uv=1) (t>t ochi1_auto ) and (autorestart=1) (uv=1) (t>t autorestart ) and (uv*=0) (uv=1) and (external_on=1) (external_on=0) external_on external external: ign, flasher, stop external_on: ign_on, flasher_on, stop_on note: * see autorestart strategy chapter. 1.4 sec min (external_on=0) (external_on=0) (external_on=0)
analog integrated circuit device data freescale semiconductor 33 35xs3500 functional device operation logic commands and registers with a calibration strategy, the output current sensing precision can be improved significantly. one calibration point at 25 c for 50% of fsr allows removing part to part contribution. so, the calibrat ed part precision goes down to +/-6.0% over [20% - 75%] out put current fsr, over voltage range (10v to 16v) and temperature range (-40 to 125 c). with dedicated calibration points, the current recopy allows diagnosing lamp damage in paralleling operations, like as flasher topology. the figure 15 summaries test results covering 99.74% of parts (device ageing not included) for standard lamps and leds. figure 15. current sense precisio n with calibration strategy board temperature feedback the 35xs3500 provides a voltage proportional to the temperature on the gnd flag . this analog feedback is available in csns output pin fo r mux[2,0] bits set to ?111?, as described in figure 16 . figure 16. analog temperature precision the board temperature feedback is not active in fail mode. with a calibration strategy, the temperature monitoring precision can be improved. so, one calibration point at 25 c allows removing part to part contribution, as presented in figure 17 . figure 17. analog temperature precision with calibration strategy output status the 35xs3500 provides the stat e of out1:out5 outputs in real time through spi. the out bi t is set to logic [1] when the corresponding output voltage is clos ed to half of battery. this bit allows synchronizing current sense and diagnosing short- circuit between out and vbat pins. temperature prewarning the 35xs3500 provides a temperature prewarning reported via the spi (otw bit) in normal mode. the information is latched. to de latch, a read spi command is needed. in case of a power on reset, the fault will be reset. external pin status the 35xs3500 provides the st atus of the flasher, ign, stop, and clock pins via the spi in real time and in normal mode. failure handling strategy a highly sophisticated failure handling strategy enables light functionality even in case of failures inside the component or the light modul e. components are protected against: ? reverse polarity ? loss of supply lines ? fatal mistreatment of logic i/o pins reverse polarity protection on v bat in case of a permanently reve rse polarity operation, the output transistors are turned on (r sd ) to prevent thermal overloads and no protections are available. an external diode on vcc is necessary in order to not to destroy the 35xs3500 in cases of reverse polarity. orange = led mode blue = lamp mode (default mode) 0 0.5 1 1.5 2 2.5 -40 -20 0 20 40 60 80 100 120 140 160 180 board tem perature (c) csns feedback (v) typ min max 0 0.5 1 1.5 2 2.5 -40 -20 0 20 40 60 80 100 120 140 160 180 board temperature (c) csns feedback (v) typ min ma x
analog integrated circuit device data 34 freescale semiconductor 35xs350 functional device operation logic commands and registers in case of negative transients on the v bat line (per iso 7637), the vcc line is still operating, while the vbat line is negative. without loads on out1:5 terminal, an external clamp between v bat and gnd is mandatory to avoid exceeding maximum rating. th e maximum external clamp voltage shall be between the reverse battery condition and -20 v. therefore, the device is prot ected against latch-up with or without load on out outputs. loss of supply lines the 35xs3500 is protected against the loss of any supply line. the detection of the supply line failure is provided inside the device itself. loss of v bat during an under-voltage of v bat (v batpor1 analog integrated circuit device data freescale semiconductor 35 35xs3500 typical applications typical applications figure 19 shows full vehicle light functionality, including fog ligh ts, battery redundancy concept, light substitution mode, and limp home mode. figure 19. typical application vcc vbat mosi, miso, sclk vcc vbat cs clock rst ign csns limp vcc vbat vcc vbat cs clock rst ign limp smart corner light switch (front right) smart corner light switch (front left) smart corner light switch (rear right) smart corner light switch (rear left) v cc (5.0v) (5.0v) wd microcontroller watchdog v bat ignition stop light v bat rea r fo g ligh t rea r dr i ve l i g h t license light sto p ligh t flasher ta i l ligh t rear fog light rear dr i ve l ight license ligh t sto p l i g ht fl a she r tail light sp are fog l ight hi g h be am l ow b eam f lash e r parking light sp are f o g l i g h t h igh b ea m lo w b e am flasher p a r k in g light csns flasher flasher stop stop cs clock rst ign csns cs clock rst ign csns limp flasher flasher limp 100nf cp cp 100nf 100nf cp cp 100nf flasher 10xs3535 10xs3535 35xs3500 35xs3500 fog fog
analog integrated circuit device data 36 freescale semiconductor 35xs350 typical applications emc & emi performances the 35xs3500 will be compliant to cispr25 class5 in standby mode with 22 nf decoupling capacitor on out[1:5].
analog integrated circuit device data freescale semiconductor 37 35xs3500 packaging packaging dimensions packaging packaging dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. pna suffix 24-pin pqfn 98art10511d issue 0
analog integrated circuit device data 38 freescale semiconductor 35xs350 packaging packaging dimensions pna suffix 24-pin pqfn 98art10511d issue 0
analog integrated circuit device data freescale semiconductor 39 35xs3500 packaging packaging dimensions pna suffix 24-pin pqfn 98art10511d issue 0
analog integrated circuit device data 40 freescale semiconductor 35xs350 revision history revision history revision date description of changes 1.0 5/2010 ? initial release 2.0 7/20101 ? changed pn to MC35XS3500PNA ? changed classification to advance information 3.0 9/2010 ? added minimum output current reported in csns for out[1-5] (12) to table 3. ? added minimum output current reported in csns for out[1-5] in led mode (12) to table 3. ? added note: output current value computed after l eakage current removal (open load condition) to table 3. 4.0 5/2011 ? added under-voltage deglitch time parameter.
how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2010-2011. all rights reserved. mc35xs3500 rev. 4.0 5/2011 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical ex perts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part.

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